Semiconductor Reliability

Semiconductor reliability is an increasing concern at advanced processes.

The drive to reduce power and costs while increasing performance is an ongoing trend, despite the end of Moore’s Law. The cost for these improvements is accelerated aging, which reduces a device’s useful life. For mission-critical applications, the industry must take a new look at reliability.

Failure modalities at the end of life for semiconductors either cause a destructive circuitry change or cause changes such that a device no longer meets specifications. Here we cover some of the main wear-out mechanisms and their specific impact on semiconductor reliability.

Semiconductor Wear-out Mechanisms

Negative Bias Temp Instability (NBTI) Hot Carrier Injection (HCI) Time Dependent Dielectric Breakdown (TDDB) Electromigration (EM)
Direct causes to chip behavior Increases P-ch threshold voltage Reduces P-ch transconductance Increase threshold voltage in both p-ch and n-ch Breakdown in gate oxide Increases resistance of conductors, eventually causes opens
Impacts to reliability Reduce logic speed Cause memory errors Reduce analog accuracy Degrade clock circuity Reduce logic speed Transistor leakage Hard failure Impact logic timing Hard failure
  • Current design flows do not account for wear out mechanisms.
  • Commercial logic libraries do not include aged library timing.
  • It is not possible to test for aging at final test.
  • Traditional semiconductor reliability programs may not capture failures.

Tartan Provides a Complete Solution for Semiconductor Reliability

Methods Traditional Solution Tartan's Solution
Follow wafer foundry specified design and layout rules Yes Yes
Subject devices to industry standard reliability testing Yes Yes
Include product traceability from wafer fab to field deployment No Yes
Include manufacturing data with device traceability to build ML algorithms for yield ramp and reliability improvement No Yes
Apply ML training to predict field failures No Yes
Device monitoring in the field, include self monitoring for failure prediction No Yes

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